In memories, individual memory cells are aligned along rows and columns. Each row has a word line to which cells along that row are attached. The cells along a row are enabled when the word line to which the cells are attached is enabled. It is important that only the word line for the selected row be enabled. Due to capacitive coupling of various clock signals with fast switching times, it is possible to enable a word line of an unselected row with capacitive coupling unless measures are taken to prevent this. This is typically achieved by clampling deselected word lines to ground which is very effective. Clamping the deselected word lines to ground requires circuitry additional to that required for a typical decoder. The clamping of deselected word lines to ground can also cause extra capacitive loading or speed problems. In U.S. Pat. No. 4,259,731, entitled "Quiet Row Selection Circuit", issued Mar. 31, 1981, assigned to the assignee hereof, an effective technique for clamping deselected word lines is disclosed. A disadvantage of the technique disclosed therein, however, is there is added capacitive loading on the gate of a word line driver transistor. This transistor is self-bootstrapped so the gate will rise above the power supply voltage. The added capacitance to the gate dilutes the bootstrap effect.
Typically, memory decoders are NOR decoders which have a relatively high input capacitance. This causes significant loading to the address buffers which provide the address signals to the decoders. The address signals are input to the gates of transistors which form the NOR decoder. The output of the NOR decoder is on the drains of these transistors. The output is thus inverted from the input. Consequently, the gate to drain capacitance is always charged between a logic high and a logic low. Consequently, a change in state of the NOR decoder not only requires that the gate to drain capacitance be charged but also discharged to the opposite polarity. This also adversely affects the speed of the decoder.